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Joint Test Action Group - JTAG is the commonly-used name for IEEE standard 1149.1, which defines a method for testing board-level interconnect - also called Boundary Scan.


JTAG-O-MAT(http://jtagomat.sourceforge.net/) provides a simple but highly flexible interface to JTAG hardware. Unlike similar projects, the focus is on running automatic JTAG sequences. It is mainly intended for bringing up virgin hardware, for use in an automated test environment, or to preload boards in a production environment. JTAG debugging is not supported. Currently supported hardware includes ARM7TDMI targets and Wiggler as well as Turtelizer programming adapters.


FJtag(http://fjtag.sourceforge.net/) is jtag management tool for Linux. Its main features include BSDL import, PCB verification, CPU and CPU bus support, Flash device programming, a script engine, and more.


AVaRICE(http://avarice.sourceforge.net/) is a program which interfaces GDB with the AVR JTAG ICE available from Atmel.

JTAG Tools

JTAG Tools(http://openwince.sourceforge.net/jtag/) is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter. This package has open and modular architecture with ability to write miscellaneous extensions (like board testers, flash memory programmers, and so on).


UrJTAG(http://www.urjtag.org/) aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It takes on the well proven openwince jtag tools code. Future plans include conversion of the code base into a library that can be used with other applications. A flexible remote communication protocol that can be used over almost any type of serial link (including TCP/IP) is currently being defined.

JTAG (Boundary Scan) Test

JTAGTest(http://www.jtagtest.com/) is an IEEE 1149.1 JTAG Boundary scan tester for embedded designers, production houses, and service companies. It provides a significant aid for PCB debugging, prototyping, testing, and repairing. Using an IEEE 1149.1 (JTAG) boundary-scan, the device pin signals or internal signals can be monitored in real-time without interfering with normal device operation, and you can change pin state manually. It runs under Wine on 32-bit Linux distributions using special Linux support libraries, which are included in the distribution.


openocd(http://openocd.berlios.de/web/) an Open on-chip JTAG debug solution for ARM7 and ARM9 systems.

inAccess Networks JTAG Tools

inAccess Networks JTAG tools(http://www.inaccessnetworks.com/projects/ianjtag) is a collection of code and a set of tools for using the JTAG interface (present in most modern microprocessors) to perform hardware tests, and for programming Flash Memory Devices connected to the processor's bus. It is especially useful for performing initial hardware tests and for bootstrapping prototype systems. It runs on a "host system" (e.g., a desktop computer with Linux) and accesses the "target system" (e.g., the embedded system's CPU board) through a simple five-line hardware interface. The host system's parallel port is used as the hardware interface, though other arrangements can be supported very easily. It is quite modular and though it currently supports the Intel StrongARM SA-1110, the Intel PXA255, and the Intel StrataFlash ICs, it can be easily extended to support other target hardware configurations by writing simple modules.

Other Resources

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